1. Field of the Invention
The present invention relates to a signal delay apparatus, a memory apparatus that utilizes this signal delay apparatus and a signal delay method, and more particularly, to a signal delay apparatus capable of providing an exact delay amount, a memory apparatus that utilizes this signal delay apparatus and a signal delay method thereof.
2. Description of the Prior Art
FIG. 1 shows a memory apparatus 100 according to the prior art. As shown in FIG. 1, the conventional memory apparatus 100 includes a memory module 101 and a control circuit 103. The control circuit 103 accesses (reads/writes) the memory chips 105-111 via signal channels 113-119. In earlier electronic apparatuses, four-layer circuit boards are utilized, so there is enough room between each signal channel line, power line and ground line. Therefore, there is no problem resulted from mismatch between signal channel lines. However, in order to decrease size and reduce cost of the electronic apparatus, two-layer circuit boards are commonly used. As a result, the signal channel lines, the power lines, the ground lines, etc. will be hard to place and route balanced, so there is a problem resulted from the mismatch between signal channel lines.
A lot of techniques are developed to solve this problem. For example, U.S. Pat. No. 4,795,923 teaches performing compensation for signal mismatch according to analog signals. Besides, U.S. Pat. No. 6,137,734 teaches selecting a correct compensation route by continuous try-and-error.
However, these techniques have shortcomings. For example, it is difficult to control the analog signal. When the compensation is realized by means of continuous try-and-error, it is time-consuming and requires a large circuit area.